High-level synthesis (HLS) is a process by which hardware designs can be generated from an algorithmic specification of the desired behavior of the hardware. A language used for the algorithmic description can be, for example, a programming language, such as C, C++ or variants thereof. Levels of abstraction in connection with hardware design can include gate level, register-transfer level (RTL) and algorithmic level. HLS starts with a high level of abstraction at the algorithmic level, where a designer specifies the algorithmic description using the appropriate programming language. The code is transformed into RTL implementations, which are then used to develop a gate level implementation.
IF-conversion is a transformation which converts control dependencies into data dependencies. Data dependencies refer to program statements that depend on data of a preceding program statement. A program instruction is control dependent on a preceding instruction if the outcome of preceding instruction determines whether the subsequent program instruction is to be executed. Condition analysis is a full-scale version of if-conversion. Non full-scale versions of if-conversion are regional and selective based on performance-gain. Full-scale if-conversion analysis is typically required for certain types of optimizations, such as HLS optimization, and concurrent very high speed integrated circuit (VHSIC) hardware description language (VHDL).